Evaluate the Effect of a High-k Gate Dielectric on MOSFET Performance Using Silvaco TCAD Simulation

Abstract

One of the significant problems with MOSFET scaling down is oxide breakdown and tunneling current. One way to address this problem is to adopt silicon-based MOSFETs with high-k dielectric materials in their gates that work well as substitutes for traditional SiO2 gates. Because high-k oxides reduce leakage and boost efficiency, these MOSFET variations can be used in low-power and high-performance applications. In the current work, the performance of the MOSFET device was studied by simulation utilizing different high-k materials, such as Si3N4, HfO2, Al2O3, and TiO2, as substitutes for the traditional SiO2 gate insulator layer. SILVACO TCAD software simulator was used to simulate the MOSFET devices for different channel lengths and gate thicknesses. The dimensions of the channel lengths with corresponding gate insulator thickness were 100 nm, 3 nm, 50 nm, 1.2 nm, and 25 nm, 0.6 nm. The simulation delved into the impacts of different configurations in device design by analyzing electrical attributes like drain current, leakage current, threshold voltage, and current ratio. The results revealed that using high k-materials with the same physical oxide thickness improved switching speed and decreased sub-threshold voltage. When the channel length and oxide thickness scaled to 1.4, an enhancement in the switching speed and stability in threshold voltage were obtained by increasing the dielectric constant of the gate oxide layer. Further reduction in the channel length and oxide layer thickness gave undesirable results.